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Signalling, DSP & Error Correction
The fraction of bits received incorrectly — and on a PAM4 link, a number that must be read pre-FEC and post-FEC separately.
BER is errored bits divided by bits sent. A BER of 1e-12 means one bit in a million million arrives wrong. The definition is trivial; what causes trouble is that on any PAM4 link there are two BER figures and they can differ by ten orders of magnitude.
Pre-FEC BER is the raw error rate on the optical and electrical path before correction. Post-FEC BER is what the Ethernet MAC actually experiences. The gap between them is not a fault or a measurement artefact — it is the whole point of forward error correction.
The target has moved too. The classic Ethernet requirement was a BER of 1e-12 at the receiver; from 200G upward 802.3 asks for 1e-13 at the MAC service interface and states it as a frame loss ratio — below 1.7e-12 for 64-octet frames on 200GBASE-CR4 — because on a FEC-protected link errors arrive in bursts of a whole codeword, not one bit at a time.
A 400G link showing a pre-FEC BER of 1e-5 and zero post-FEC errors is working exactly as specified. It is not degraded, it does not need a new module, and swapping the optic will produce an identical number. Reacting to pre-FEC counts as though they were post-FEC counts is the single most common way healthy transceivers get returned.
What actually matters is margin and direction. A lane at 1e-6 has more than two decades of headroom before KP4 runs out; one at 5e-5 has well under one. Because the failure at the end is abrupt, the absolute number matters far less than whether it has moved since last week.
A zero-error test does not prove a BER of zero, only an upper bound. With no errors observed the 95 per cent confidence bound is about three divided by the number of bits tested, so demonstrating 1e-12 takes roughly three million million bits — about eight seconds at 400G, but several minutes at 10G.
This is why short soak tests prove very little on slow links and quite a lot on fast ones, and why a supplier quoting an error-free burn-in should be able to say for how long and at what rate. Tier 1 and Tier 2 testing covers the equivalent question for the fibre plant.
Pre-FEC BER combined with the DDM optical power readings will usually localise a problem between them. Receive power low and errors high points at the fibre plant — loss, a bend, a bad splice. Receive power normal and errors rising points at a dirty end face, a marginal transmitter or a host channel that is not training well.
Errors on one lane of a parallel module and not the others point at one fibre or one ferrule position, which is a cleaning job rather than a module swap; see end-face inspection. The link-down diagnostic guide works through the sequence, and the power converter helps when the counters and the datasheet disagree about units.
| Definition | errored bits divided by bits transmitted |
|---|---|
| Post-FEC target | 1e-12 on legacy PMDs; 1e-13 at the MAC, or the frame-loss-ratio equivalent, from 200G up |
| Typical pre-FEC on a healthy PAM4 lane | 1e-6 to 1e-5 |
| KP4 correction limit | about 2.4e-4 pre-FEC with random errors |
| Equivalent PAM4 symbol error ratio | about 4.8e-4 |
| Bits needed to prove 1e-12 with no errors | about 3e12, at 95 per cent confidence |
| Time that takes at 400G | roughly 8 seconds |
| Time that takes at 10G | roughly 5 minutes |
| Where to read it | switch interface FEC counters, not the module's DDM page |
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