The serialiser/deserialiser in the switch ASIC that turns parallel internal data into the high-speed serial lanes a transceiver consumes.
What a SerDes Is
A switch ASIC moves data internally on very wide, comparatively slow parallel buses. A transceiver or a direct-attach cable accepts a small number of very fast serial lanes. The serialiser/deserialiser is the block that converts between the two worlds, and its per-lane rate is the single most consequential number in a switching platform.
It is not a detail buried in the silicon. The SerDes generation decides how many lanes a port of a given speed consumes, which decides the number of optical channels, which decides the fibre count, the module power and the form factor. Everything on the faceplate is downstream of it.
Serialising Is the Easy Part
Most of a modern SerDes is equalisation. On transmit a feed-forward equaliser pre-distorts the waveform so that what arrives at the far end is closer to square than what left. On receive a continuous-time linear equaliser flattens the broad frequency response and a decision-feedback equaliser cancels the residual tail of each symbol using the decisions already made.
The better that machinery is, the less work the module has to do — which is precisely the premise linear pluggable optics is built on. Delete the module DSP and the host SerDes inherits the entire job, so an LPO link is only as good as the SerDes at each end.
The Arithmetic That Reaches the Faceplate
At 112G per lane, 400G takes four lanes and 800G takes eight. At 224G per lane, 400G takes two and 800G takes four. Halving the lane count for the same port speed halves the optical channels, and usually the fibre count with them.
It also constrains what a switch can physically offer. A platform whose SerDes stop at 56G cannot support QSFP112, because QSFP112 is four lanes of 112G by definition. When two switches with the same headline capacity offer different cage types, the SerDes generation is usually the reason — see OSFP versus QSFP-DD.
Where You Meet It
In every breakout decision. A port divides cleanly by one, two, four or eight because that is how many SerDes lanes it owns; the breakout configurator is really a lane-arithmetic tool wearing a friendlier name.
You also meet it when a link trains badly. Long host traces, a marginal cage or an aggressive cable length can push a lane past what its equaliser can recover, and the symptom is a link that comes up and then flaps under load rather than one that fails outright. Our SerDes explainer works through the generations in more detail.
SerDes generations and what they mean
| 28G NRZ | 25.8 GBd — 100G needs 4 lanes |
|---|---|
| 56G PAM4 | 26.6 GBd — 400G needs 8 lanes |
| 112G PAM4 | 53.1 GBd — 400G needs 4, 800G needs 8 |
| 224G PAM4 | 106.25 GBd — 800G needs 4, 1.6T needs 8 |
| Transmit equalisation | feed-forward, a few taps |
| Receive equalisation | CTLE plus decision-feedback, increasingly with FFE |
| OIF reach classes | XSR die-to-engine, VSR chip-to-module, MR on PCB, LR over backplane |
| Host interface name | AUI-C2M, the chip-to-module attachment unit interface |
Related Terms
224G SerDes is the next generation; NRZ and PAM4 are the two things a lane can carry.