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Tech Explained

224G SerDes: The Physical-Layer Change Behind 1.6T and 3.2T

FOT Engineering Team·2026-07-30·9 min read
In this article→ The Arithmetic That Decides Everything→ Why 112 Gigabaud Barely Survives a Circuit Board→ What It Does to Optics, Fibre and Power→ The Collision With Linear Optics→ What to Plan For→ FAQ

Every speed generation is announced as a bandwidth doubling, and every generation the decision that actually matters is made one level down, at the lane. 224G SerDes — roughly 200 gigabits of payload per electrical lane — is the change that defines the 1.6T generation, and it is considerably harder than the doubling before it.

The Arithmetic That Decides Everything

Port speed is lanes multiplied by lane rate, and the industry has alternated between increasing each.

100G to 1.6T: the lane count moved once, from four to eight. Everything since has been lane rate — except OSFP-XD, which goes wide instead.
100G to 1.6T: the lane count moved once, from four to eight. Everything since has been lane rate — except OSFP-XD, which goes wide instead.

At 112G SerDes, 1.6T needs sixteen lanes. At 224G it needs eight. That halving cascades: half the optical channels, half the lasers and detectors, half the fibre in the cable, and better power per bit. It is why OSFP-XD — sixteen lanes at 100G — and OSFP224 — eight lanes at 200G — both reach 1.6T while being very different propositions.

Why 112 Gigabaud Barely Survives a Circuit Board

The modulation stays PAM4, so doubling the lane rate roughly doubles the symbol rate to around 112 gigabaud. At those frequencies, things that were second-order become dominant: dielectric loss in the board material, reflections at every connector and via, package parasitics, and crosstalk between adjacent lanes.

The practical consequence is that the electrical channel a 224G lane can cross is short. Not "shorter than before" — short in absolute terms, measured against the distance from a switch ASIC in the middle of a board to a cage at the faceplate.

This is the real reason co-packaged and near-packaged optics moved from research curiosity to roadmap item so quickly. It is not primarily about power. It is that at 224G the board itself is running out of margin, and moving the optics to the ASIC is the most direct way to delete the problem.

What It Does to Optics, Fibre and Power

Fibre count halves for the same bandwidth. An eight-lane 1.6T DR8 needs sixteen fibres; a sixteen-lane OSFP-XD equivalent needs thirty-two. Over a large plant that is a substantial difference in trunk cable — work it out for your own port count in the cabling planner.

Power per bit improves, power per port does not. Fewer, faster lanes is more efficient per gigabit, but a 1.6T port still lands around 28 watts. A 32-port switch fully populated is dissipating nearly a kilowatt in transceivers alone. Check what that does to your rack budget in the power and thermal calculator before the design is fixed.

DSP work goes up, not down. Equalising a 112 gigabaud channel is harder than equalising a 56 gigabaud one, so the DSP has more to do and burns more doing it.

The Collision With Linear Optics

That last point creates a genuine tension worth understanding, because it is where the 1.6T generation is unresolved.

Linear pluggable optics works by deleting the module's DSP and relying on the host SerDes to do the equalisation. That premise gets harder exactly as lane rates rise: at 224G there is less margin to give away, and the host has more work to do already.

So two things are pushing in opposite directions at 1.6T. Power pressure pushes toward removing DSPs; signal integrity pressure pushes toward keeping them and shortening the channel instead. Co-packaging resolves the tension by doing both — keep the DSP, delete the board. Which is a large part of why it is being taken seriously now rather than in five years. Our comparison of the four approaches works through the trade-offs.

What to Plan For

Ask which SerDes generation a platform has. It determines which form factors the switch can offer. A platform whose SerDes top out at 112G cannot give you OSFP224 or QSFP112, whatever the cage looks like.

Do not over-build fibre for a lane count that may halve. If your 1.6T deployment is two years out and could land on 224G rather than 112G lanes, the fibre requirement differs by a factor of two. Base-16 MPO plant serves both cases cleanly, which makes it the low-regret choice — see base-8 vs base-12 vs base-16.

Assume the reach classes stay the same. DR, FR and LR mean the same distances at 1.6T as at 800G. The lane rate changes what happens inside the module and on the board, not what happens in the fibre.

FAQ

Is 224G SerDes shipping? It is arriving in switch silicon and in first-generation 1.6T modules. Whether OSFP224 or OSFP-XD dominates at 1.6T depends largely on how fast 224G reaches volume, and both are being built.

Does 224G change the fibre I install? Not the glass — single-mode is single-mode. It changes how much of it you need, because lane count drives fibre count.

Why not just add more lanes instead? That is exactly what OSFP-XD does, and it works. The cost is a great deal more fibre, more optical components and more power per port. Fewer, faster lanes is the better long-term answer; wider is the answer available sooner.

What comes after 224G? 448G per lane is being discussed, and it is a very hard problem — at which point optical interconnect much closer to the silicon stops being optional.

Keep Reading

📄 1.6T Optical Interconnect: OSFP-XD, 200G Lanes and What Actually Ships in 2026📄 LPO vs CPO vs NPO: Which 1.6T Switch Architecture Should You Actually Cable For?📄 Ultra Ethernet vs RoCE: What UEC Actually Changes for AI Fabrics

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